1. Field of the Invention
The invention relates to phase lock loops in general and more particularly to apparatus for centering the Voltage Control Oscillator (VCO).
2. Prior Art
The use of phase lock loops in various types of communication systems is well known in the prior art. A typical phase lock loop consists of a phase comparator, a loop filter and a voltage controlled oscillator (VCO). The phase comparator compares the phase of an input reference signal with the phase of the VCO and generates an error voltage which is used to drive the VCO until it is phase locked with the input reference signal. It is desirable to have as large a dynamic range of correction voltage as possible. This would allow the maximum correction for phase transients and frequency variations in the reference signal.
In integrated circuit technology, design of VCO circuits usually has a variation in the natural frequency (f.sub.c) of .+-.8%. In addition, the timing capacitor which is an integral part of the VCO usually has a tolerance of .+-.5%. As a result, the VCO natural frequency will vary by .+-.13%. The variation means that as the PLL locks onto an input signal, at a particular frequency, the VCO will be forced to that frequency by an adjustment in the correction voltage at its input. This consumes a large part of the available voltage range and limits the dynamic range of the PLL for tracking phase and/or frequency changes in the incoming signal.
In the past using up a large part of the available voltage range presents no problems since linear circuits were designed using voltages with a potential difference of at least 10 volts. In cases where the optimum range was required, a potentiometer was used to adjust the VCO to the desired frequency when the input voltage was at the center of the allowed range.
There are several technologies in which the range of voltages available for adjusting the VCO is relatively narrow. For example, in a VLSI chip a potential difference of 4.5 volts or less is available. In addition, there is an effort in the CMOS technology to design chips comprising of logic circuits, processors and memories. It is believed that these designs will probably have a larger variation in the natural frequency (f.sub.c) of the VCO. In fact, it is believed that as the integration and/or compaction of devices on a single chip increase, the variation in the natural frequency of the VCO will also increase. The use of a potentiometer to manually set the center frequency is very undesirable. With the variation in the natural frequency of the VCO and the limited range for the correction voltage, it is obvious that some efficient method is needed to adjust the center frequency of the VCO.